Conventionally, a transmission system comprises an electronic transmitter, a transmission channel and an electronic receiver. The transmission channel may consist of any medium used for data transfer. In particular, physical lines are used. But a wireless channel is also conceivable, wherein data transfer is accomplished through electromagnetic radiation.
The electronic transmitter usually comprises a clock generator as well as a transmitting unit. Information is encoded bitwise and each bit is synchronized with the transmitter clock. In particular, the transmitter may output a relatively high voltage representative of a bit 1 and a relatively low voltage representative of a bit 0 on a transmission line. Transitions from a high to a low voltage and vice versa are both synchronized with respective up transitions of the clock signal. The high bit voltage as well as the low bit voltage are transferred during a period of the clock, in order to transmit a single bit.
The transferred signal is recovered by the receiver. The receiver comprises a clock and a receiving unit. In particular, the clock is recovered from the transferred data using a phase locked loop. The transferred bits are sampled in synchronism with the clock. The ideal sampling point for bit recovery lies halfway between two consecutive edges of the recovered clock. Therefore, the sampling points are phase shifted by T/2 in relation to the clock transitions.
Due to the attenuation and delay characteristics of the transmission channel, jitter occurs on this side of the receiver. Jitter stands for the deviation of an event from the ideal timing of the event. In the instance of a data communication system, the event recorded is the transition of the received data signal. The ideal timing of this event is in synchronism with the clock transitions provided by the recovered clock. However, as a result of jitter the received data transitions do not occur simultaneously with the clock transitions.
The problem of jitter has been addressed in the state of the art concerned with data transmission. In particular, a certain kind of data dependent jitter, namely inter-symbol-interference (ISI) has been recognized. The X-axis of the coordinate system shown in FIG. 1 represents time and the Y-axis the voltage of the received signals. Signal 1 represents the received wave form, which is detected, if a bit pattern 11110 is transmitted. Signal 2 results from a bit pattern 00010. The initial voltage value of signal 1 represents a high voltage state corresponding to a high bit, whereas an initial state of signal 2 is the opposite, namely a low voltage state representative of a low bit. A horizontal line between the two initial states of signals 1 and 3 represents the intermediate voltage in the center between the initial state of the first and second signal. Signal 1 eventually descends down to the low voltage state, whereby it intersects the intermediate state. Signal 2 rises above the intermediate state, but does not reach the high voltage binary state. Instead, signal 2 descends down to its initial state, before reaching the high voltage state. Because of the attenuation and the delay of the transmission channel, both signals 1 and 2 do not intersect the intermediate state during a top down transition at the same point in time. The inter-symbol-interference time skew TISI is representative of the jitter caused by inter-symbol-interference. The reason for inter-symbol-interference is that signal 2 does not reach the voltage level, from which signal 1 descends. The effect of inter-symbol-interference is an increased bit error ratio (BER) on the side of the receiver.
A state of the art solution to the problem of inter-symbol-interference in data transmission systems consists of providing four different voltage levels for transmitting signals on the side of the transmitter. The two intermediate voltage levels of the four voltage levels correspond to the up and down voltage states conventionally used. A further higher and lower voltage state is also provided for transmission. Each time a transition from a low to a high bit is to be transferred, the transmitter chooses a voltage level having an increased amplitude for transmitting said bit sequence transition. Signal 3 in FIG. 1 shows the resulting waveform for the bit pattern 00010 (bit pattern of signal 2). Since the high bit is transferred with an added voltage amplitude, the received waveform rises to a far higher level than signal 2. Consequently, the intersection between the falling edge of signal 3 and the intermediate level shown in FIG. 1 is almost synchronous with the intersection between the signal 1 and the intermediate level. The inter-symbol-interference skew has been improved. However, the pre-emphasis of the voltage amplitude leads to increased power consumption on the side of the transmitter. Furthermore, additional jitter may occur if pre-emphasis over compensates the attenuation on the transmission line or if the pre-emphasis compensation is insufficient.